Agentic verification
for chip design

Siltrace Agent

Why

Only 5% of chip projects succeed on the first tapeout1

PRE-SILICONPOST-SILICONSpecRTL designVerificationPhysical designTapeoutFabricationFirst silicon~50%of project time is verification 1$40M+per advanced mask set 26–12 moof delay per re-spin 2 PRE-SILICONPOST-SILICONSpecRTL designVerificationPhysical designTapeoutFabricationFirst silicon~50%of project time is verification 1$40M+per advanced mask set 26–12 moof delay per re-spin 2 PRE-SILICONPOST-SILICONSpecRTL designVerificationPhysical designTapeoutFabricationFirst silicon~50%of project timeis verification 1$40M+per advancedmask set 26–12 moof delayper re-spin 2

How

Verification expertise, encoded into the harness

Knowledge

Tools

Know-how

Experience

INSpecRTLOUTVerified RTLProven fixPlanProposeCheckLearnINSpecRTLOUTVerified RTLProven fixProposeCheckLearnPlan

Proof

Beats the best on public benchmarks3

HWE-Bench

Bugs fixed, of 172

Siltrace AgentGPT-6.1 Sol

170

Claude Code + Siltrace EngineOpus 5.5

165

Claude CodeOpus 5.5

162

CodexGPT-6.1 Sol

157

CodexGPT-6 Astra

156

CirFix

Wrong fixes passed as correct

Official tests

28

Siltrace

0

VerilogEval v2

Empty designs passed as correct

NVIDIA’s grader

152

Siltrace

0

Vision

From verification to the whole chip lifecycle

CHIP LIFECYCLEPRE-SILICONPOST-SILICONTAPEOUTSpec andarchitectureRTL andIP designVerificationPhysicaldesignFabricationProductiontestIn thefieldNEXTDesign agentsGenerate proven RTL and IPNOWVerification agentsFind missed bugs, prove every fixNEXTPost-silicon agentsField diagnosis and screeningSiltrace agent platform